Low Power Nanoscale RF/Analog MOSFETs

被引：0
|
作者：
Ghoshi, Dipankar [1 ]
Parihar, Mukta Singh [1 ]
Armstrong, G. Alastair [2 ]
Kranti, Abhinav [1 ]
机构：
[1] Indian Inst Technol Indore, Low Power Nanoelect Res Grp, Indore 452017, Madhya Pradesh, India
[2] Queens Univ Belfast, Sch Electron, Elect Engn & Comp Sci, Belfast BT7 1NN, Antrim, North Ireland
来源：
2012 12TH IEEE CONFERENCE ON NANOTECHNOLOGY (IEEE-NANO) | 2012年
关键词：
Low power; Analog/RF; Linearity; Double Gate MOSFET; PERFORMANCE; IMPACT;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
The present work reports on the substantial benefits of underlap SourcelDrain (SID) design in moderately inverted nanoscale MOSFETs to significantly enhance key analog/RF performance metrics. It is demonstrated that underlap SID design alleviates the inherent trade-ofrs between bandwidth, gain and linearity for low power RF CMOS nanodevices. Optimal underlap region parameters are identified and design trade-ofrs examined. The results are significant for RFICs with nanoscale MOSFETs in emerging technologies.
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页数：4
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