3D Scaling for Insulated Gate Bipolar Transistors (IGBTs) with Low Vce(sat)

被引：0

作者：

Tsutsui, K. ^{[1
]}

Kakushima, K. ^{[1
]}

Hoshii, T. ^{[1
]}

Nakajima, A. ^{[2
]}

Nishizawa, S. ^{[3
]}

Wakabayashi, H. ^{[1
]}

Muneta, I. ^{[1
]}

Sato, K. ^{[4
]}

Matsudai, T. ^{[5
]}

Saito, W. ^{[5
]}

Saraya, T. ^{[6
]}

Itou, K. ^{[6
]}

Fukui, M. ^{[6
]}

Suzuki, S. ^{[6
]}

Kobayashi, M. ^{[6
]}

Takakura, T. ^{[6
]}

Hiramoto, T. ^{[6
]}

Ogura, A. ^{[7
]}

Numasawa, Y. ^{[7
]}

Omura, I. ^{[8
]}

Ohashi, H. ^{[1
]}

Iwai, H. ^{[1
]}

机构：

[1] Tokyo Inst Technol, Yokohama, Kanagawa, Japan

[2] Natl Inst Adv Ind Sci & Technol, Tsukuba, Ibaraki, Japan

[3] Kyushu Univ, Fukuoka, Japan

[4] Mitusbishi Elect, Fukuoka, Japan

[5] Toshiba Elect Devices & Storage Corp, Tokyo, Japan

[6] Univ Tokyo, Tokyo, Japan

[7] Meiji Univ, Kawasaki, Kanagawa, Japan

[8] Kyushu Inst Technol, Kitakyushu, Fukuoka, Japan

来源：

2017 IEEE 12TH INTERNATIONAL CONFERENCE ON ASIC (ASICON) | 2017年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Three dimensionally (3D) scaled IGBTs that have a scaling factor of 3 (k=3) with respect to current commercial products (k=1) were fabricated for the first time. The scaling was applied to the lateral and vertical dimensions as well as the gate voltage. A significant decrease in ON resistance, -1 V-ce(sat) reduction from 1.70 to 1.26 V -- was experimentally confirmed for the 3D scaled IGBTs.

引用

页码：1137 / 1140

页数：4

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