Hardware Implementation of a High Speed Floating Point Multiplier Based on FPGA

被引：4

作者：

Gong Renxi ^{[1
]}

Zhang Shangjun ^{[2
]}

Zhang Hainan ^{[1
]}

Meng Xiaobi ^{[1
]}

Gong Wenying ^{[1
]}

Xie Lingling ^{[1
]}

Huang Yang ^{[1
]}

机构：

[1] Guangxi Univ, Sch Elect Engn, Nanning 530004, Peoples R China

[2] Guilin Coll Aerosp Technol, Dept Elect Engn, Guilin 541004, Peoples R China

来源：

ICCSSE 2009: PROCEEDINGS OF 2009 4TH INTERNATIONAL CONFERENCE ON COMPUTER SCIENCE & EDUCATION | 2009年

关键词：

FPGA; Booth's algorithm; Partial Product Compression; Pipeline; Floating-point Multiplier;

D O I：

10.1109/ICCSE.2009.5228240

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

The hardware implementation of a high speed floating point multiplier with pipeline architecture based on FPGA is presented in the paper. In the design of the floating point multiplier, the utilization of a new Radix-4 Booth's encoding algorithm, the improved 4:2 compression structure and summation circuit is made to implement the compression of the partial products, and the sum and carry vectors are added by a final carry look-ahead adder to obtain the product. The timing simulation results show that the floating point multiplier can be steadily run at the frequency of 80 MHz. The multiplier has been adopted in the FFT processor successfully.

引用

页码：1902 / +

页数：2

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