FPGA Based Implementation of a Floating Point Multiplier and its Hardware Trojan Models

被引：1
|
作者：
Nikhila, S. [1 ]
Yamuna, B. [1 ]
Balasubramanian, Karthi [1 ]
Mishra, Deepak [2 ]
机构：
[1] Amrita Vishwa Vidyapeetham, Amrita Sch Engn, Dept Elect & Commun Engn, Coimbatore, Tamil Nadu, India
[2] ISRO, Space Applicat Ctr SAC, Digital Commun Div DCD, Ahmadabad, Gujarat, India
来源：
2019 IEEE 16TH INDIA COUNCIL INTERNATIONAL CONFERENCE (IEEE INDICON 2019) | 2019年
关键词：
floating point number; single precision; hardware Trojans;
D O I：
10.1109/indicon47234.2019.9030341
中图分类号：
TP39 [计算机的应用];
学科分类号：
081203 ; 0835 ;
摘要：
Floating point multiplication plays a crucial role in computationally intensive applications like digital signal processing. This paper deals with the design of a single precision floating point multiplier and its FPGA realization with LCD interface for output display. To bring out the need for secure hardware design, hardware Trojan models are proposed for the mantissa multiplication unit of the floating point multiplier. Implementation results show that the Trojans produce an average difference of 15%-20% in the product values, an increase of onchip power by 1.61% and an increase of 0.4% in the number of LUTs. The negligible change in the area and power dissipated establishes the stealthy nature of the proposed Trojans.
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页数：4
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