共 39 条
- [21] Non-Binary Low-Density Parity-Check Codes for the q-ary Erasure Channel 2013 IEEE INTERNATIONAL CONFERENCE ON COMMUNICATIONS (ICC), 2013, : 3258 - 3263
- [22] Trellis Based Check Node Processing For Nonbinary LDPC Decoding Using Power Representation 2016 FIRST IEEE INTERNATIONAL CONFERENCE ON COMPUTER COMMUNICATION AND THE INTERNET (ICCCI 2016), 2016, : 99 - 102
- [23] Low-density parity-check codes with rates very close to the capacity of the q-ary symmetric channel for large q 2004 IEEE INTERNATIONAL SYMPOSIUM ON INFORMATION THEORY, PROCEEDINGS, 2004, : 275 - 275
- [24] A parallel sliding-window belief propagation algorithm for Q-ary LDPC codes accelerated by GPU Multimedia Tools and Applications, 2020, 79 : 34287 - 34300
- [25] A new Architecture for High Throughput, Low Latency NB-LDPC Check Node Processing 2015 IEEE 26TH ANNUAL INTERNATIONAL SYMPOSIUM ON PERSONAL, INDOOR, AND MOBILE RADIO COMMUNICATIONS (PIMRC), 2015, : 1392 - 1397
- [26] Self-Adaptive Termination Check of Min-Sum Algorithm for LDPC Decoders Using the First Two Minima KSII TRANSACTIONS ON INTERNET AND INFORMATION SYSTEMS, 2017, 11 (04): : 1987 - 2001
- [27] EFFICIENT CHECK NODE PROCESSING ARCHITECTURES FOR NON-BINARY LDPC DECODING USING POWER REPRESENTATION 2012 IEEE WORKSHOP ON SIGNAL PROCESSING SYSTEMS (SIPS), 2012, : 137 - 142
- [28] Low-complexity Check Node Processing for Trellis Min-max Nonbinary LDPC Decoding 2018 INTERNATIONAL CONFERENCE ON ADVANCED TECHNOLOGIES FOR COMMUNICATIONS (ATC), 2018, : 292 - 295
- [29] Efficient Check Node Processing Architectures for Non-binary LDPC Decoding Using Power Representation Journal of Signal Processing Systems, 2014, 76 : 211 - 222
- [30] Efficient Check Node Processing Architectures for Non-binary LDPC Decoding Using Power Representation JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, 2014, 76 (02): : 211 - 222