DEVICE DESIGN BASED ON LOW-NOISE PARALLEL-FIELD HALL SENSOR

A new approach for reducing the internal 1/f noise in parallel-field Hall microsensors with minimal design complexity was suggested and experimentally tested. The Hall structure consist n-Si substrate and three n(+)-strip contacts which are placed on the one chip surface. An important peculiarity of the design necessary to overcome the noise problem is the location of the sense contact outside the zone in which the supply current flows. The internal noise of this case is at least 10 times smaller than those of the three-contact device with an inside placed Hall terminal. The resolution is enhanced and reaches 35 mu T at a current 4 mA over a 5-500 Hz bandwidth. The sensor performance proved undoubtedly that the new approach to reducing the 1/f noise is very promising.