Design of Low-Power Low-noise CMOS ECG Amplifier for Smart Wearable Device

The artificial intelligence health care devices have focused on the portability and accuracy and the most trending area of wearable biomedical application has become the electrocardiogram (ECG) recording device. The ECG signals have the characteristic of low amplitude, prone to be influenced by Power Line Interference (PLI), so it is essential to achieve high gain and high common-mode rejection ratio (CMRR),while the input-referred noise and power consumption need to be low to realize the cardiac screening system on chip (Soc).In this paper, a low-noise low-power analog front end (AFE) amplifier which based on Driven-RightLeg circuit(DRL) has been proposed. It was implemented in CMOS 180 nm with bias current and supply voltage of 12 mu A and 0.7V, respectively. The simulation results showed that this front-end circuit can achieve a low input referred noise of 4.11 mu V/Hz and high common mode rejection ratio of 135dB. It also gave voltage gain of 41.8 dB with the bandwidth from 0.1Hz to 100Hz and the total power consumption was 4.32 mu W. Compared with recently relevant whole circuit design, we believe that it is suitable to be used in smart wearable device.