A 3D NAND Flash Ready 8-Bit Convolutional Neural Network Core Demonstrated in a Standard Logic Process

被引:36
|
作者
Kim, M. [1 ]
Liu, M. [1 ]
Everson, L. [1 ]
Park, G. [1 ]
Jeon, Y. [2 ]
Kim, S. [2 ]
Lee, S. [2 ]
Song, S. [2 ]
Kim, C. H. [1 ]
机构
[1] Univ Minnesota, Dept ECE, Minneapolis, MN 55455 USA
[2] ANAFLASH Inc, San Jose, CA USA
关键词
D O I
10.1109/iedm19573.2019.8993574
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A convolutional neural network (CNN) core that can be readily mapped to a 3D NAND flash array was demonstrated in a standard 65nm CMOS process. Logic compatible embedded flash memory cells were used for storing multi-level synaptic weights while a bit-serial architecture enables 8 bit multiply-and-accumulate operation. A novel back-pattern tolerant program-verify scheme reduces the cell current variation to less than 0.6 mu A. Positive and negative weights are stored in eFlash cells in adjacent bitlines, generating a differential output signal. Our eNAND based neural network core achieves a 98.5% handwritten digit recognition accuracy which is close to the software accuracy of 99.0% for the same precision. This work represents the first physical demonstration of an embedded NAND Flash based neuromorphic chip in a standard logic process.
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页数:4
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