VERBUS: A formal model for business process verification

被引:0
|
作者
Fisteus, JA [1 ]
Lopez, AM [1 ]
Kloos, CD [1 ]
机构
[1] Univ Carlos III Madrid, Telemat Engn Dept, Leganes 28911, Madrid, Spain
关键词
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暂无
中图分类号
F [经济];
学科分类号
02 ;
摘要
Business process management is a key issue in B2B. Different process modelling languages and workflow management tools and frameworks have appeared to aid the development, deployment and management of e-commerce solutions. Nevertheless, there is not yet a framework to compel with tasks such as guaranteeing: safety outcomes of the run of a composition of processes, the eventual execution of processes under some condition, or the soundness of a design with respect to the specification. This is the mission of format methods. and they have been successfully applied in the fields of real-time software, hardware verification, and a growing list of application areas as the computation costs decrease. In this article we present VERBUS, a formal system for the modelling and verification of business processes. VERBUS allows a designer to specify properties for verification. The Finite State Machine theory is under the hood of VERBUS, providing the designer with a well-known and understandable approach, which offers a set of existing tools for verification or for compiling to other formats for the application of model-checkers.
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页码:238 / 241
页数:4
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