Low spurious frequency setting algorithm for a triple tuned type PLL synthesizer driven by a DDS

被引：0

作者：

Tajima, K ^{[1
]}

Imai, Y

Kanagawa, Y

Itoh, K

Isota, Y

Ishida, O

机构：

[1] Mitsubishi Electr Corp, Kamakura, Kanagawa 2478501, Japan

[2] Mitsubishi Electr Corp, Amagasaki, Hyogo 6618661, Japan

来源：

IEICE TRANSACTIONS ON ELECTRONICS | 2002年 / E85C卷 / 03期

关键词：

direct digital synthesizer; phase locked loop; spurious component; triple tune;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This letter presents a low spurious frequency setting algorithm for a triple tuned type PLL synthesizer driven by a DDS. The triple tuned PLL synthesizer is based on a single PLL configuration with two variable frequency dividers. The DDS is employed for a reference source of the PLL. The proposed algorithm determines appropriate frequency tuning values of the DDS frequency and the division ratios of two frequency dividers. The division ratios are selected to achieve a desired output frequency while the low spurious condition of the DDS has been maintained. A 5 to 10 GHz synthesizer with frequency step of 500 kHz demonstrated spurious level below -46 dBc with improvement of 13 dB.

引用

页码：595 / 598

页数：4

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