A 1-GS/s 6-bit folding and interpolating ADC in 0.13-μm CMOS

被引：6
|
作者：
Lin, Li [1 ]
Ren, Junyan [1 ]
Zhu, Kai [1 ]
Ye, Fan [1 ]
机构：
[1] Fudan Univ, State Key Lab ASIC & Syst, Micro Nano Elect Innovat Platform, Shanghai 201203, Peoples R China
来源：
ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING | 2009年 / 58卷 / 01期
关键词：
Analog-to-digital converter; CMOS analog integrated circuits; Folding; Interpolating;
D O I：
10.1007/s10470-008-9222-5
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
A 1-GS/s 6-bit two-channel time-interleaved folding and interpolating analog-to-digital converter (ADC) is presented in this article. For low voltage applications, input-connection-improved active interpolating amplifiers and cascaded folding amplifiers have been applied. A single front-end track-and-hold (T/H) circuit is used to avoid the sampling-time mismatches between the channels. When supplied with 1.4 V, the circuit achieves signal-to-noise-plus-distortion ratio (SNDR) of 30.74 dB and spurious free dynamic range (SFDR) of 36.91 dB and consumes a power of 66 mW with 500-MHz input and 1-GS/s sampling rate. Differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.57 and 0.81 LSB, respectively. The figure of merit (FoM) is 1.75 pJ/conversionstep. The ADC circuit is prototyped in 0.13-mu m CMOS process and occupies a core area of 0.45 mm(2).
引用
收藏
页码：71 / 76
页数：6
相关论文
共 50 条
  • [31] A 2 GS/s 8-bit folding and interpolating ADC in 90 nm CMOS
    贺文伟
    孟桥
    张翼
    唐凯
    Journal of Semiconductors, 2014, 35 (08) : 144 - 148
  • [32] 6-bit 1.6GS/s ADC with low input capacitance in a 0.18μm CMOS
    Chen, Chun-Chieh
    Chung, Yu-Lun
    Chiu, Chen-I
    2009 1ST ASIA SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, 2009, : 288 - 291
  • [33] A 'digital' 6-bit ADC in 0.25μm CMOS
    Donovan, C
    Flynn, MP
    PROCEEDINGS OF THE IEEE 2001 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 2001, : 145 - 148
  • [34] A 65mW 1.2Gsamples/s 6-bit flash ADC in 0.13μm CMOS
    Wang, Ke
    Skafidas, Efstratios
    Evans, Rob
    WSEAS Transactions on Circuits and Systems, 2006, 5 (09): : 1409 - 1415
  • [35] A Design of 6-bit125-MS/s SAR ADC in 0.13-μm MM/RF CMOS Process
    Rajasekar, R.
    Ramakrishna, P. V.
    2012 INTERNATIONAL SYMPOSIUM ON ELECTRONIC SYSTEM DESIGN (ISED 2012), 2012, : 23 - 27
  • [36] A 10-bit 1-GS/s CMOS ADC with FOM=70 fJ/Conversion
    Hashemi, Sedigheh
    Razavi, Behzad
    2012 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC), 2012,
  • [37] A 1-V 1-GS/s 6-bit Low-Power Flash ADC in 90-nm CMOS with 15.75 mW Power Consumption
    Lad, Kirankumar
    Bhat, M. S.
    2013 INTERNATIONAL CONFERENCE ON COMPUTER COMMUNICATION AND INFORMATICS, 2013,
  • [38] A 0.13-μm 1-GS/s CMOS Discrete-Time FFT Processor for Ultra-Wideband OFDM Wireless Receivers
    Lehne, Mark
    Raman, Sanjay
    IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, 2011, 59 (06) : 1639 - 1650
  • [39] A "digital" 6-bit ADC in 0.25-μm CMOS
    Donovan, C
    Flynn, MP
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2002, 37 (03) : 432 - 437
  • [40] A 8-Bit 1-GS/s Subranged ADC in 65-nm CMOS Process
    Chen, Hsin-Liang
    Yang, Shu-Chuan
    2015 INTERNATIONAL SYMPOSIUM ON INTELLIGENT SIGNAL PROCESSING AND COMMUNICATION SYSTEMS (ISPACS), 2015, : 40 - 43
12345