A two-item floating point fused dot-product unit with latency reduced

被引：0

作者：

Wang, Mingjiang ^{[1
]}

Liu, De ^{[1
]}

Liu, Ming ^{[1
]}

Zhao, Boya ^{[1
]}

机构：

[1] Harbin Inst Technol, Shenzhen Grad Sch, Shenzhen 518055, Guangdong, Peoples R China

来源：

IEICE ELECTRONICS EXPRESS | 2016年 / 13卷 / 23期

关键词：

floating point arithmetic; fused dot-product unit; fused FFT-butterfly unit; ADD-SUBTRACT UNIT; IMPROVED ARCHITECTURES;

D O I：

10.1587/elex.13.20160937

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a floating point fused dot-product (FDP) unit with latency reduced. The proposed FDP unit performs the dot-product operation of four floating point numbers: ab +/- cd and is implemented with dual-path algorithm. The proposed FDP is modeled in Verilog-HDL and synthesized using TSMC 65 nm technology library. Synthesis results show that our proposed FDP unit is 24 similar to 30% faster and 36.4% less area than the fastest FDP in previous work. We also use the proposed FDP unit and our previously designed FAS (fused add-subtract) unit to implement a FFT Radix-2 Butterfly (R2BF) unit. The latency of our proposed R2BF unit is improved roughly by 34% and the area is reduced by 41.6%, compared to the fastest 2' s-complement butterfly unit.

引用

页数：12

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