Correlation between static random access memory power-up state and transistor variation

被引：6

作者：

Takeuchi, Kiyoshi ^{[1
]}

Mizutani, Tomoko ^{[1
]}

Saraya, Takuya ^{[1
]}

Shinohara, Hirofumi ^{[2
]}

Kobayashi, Masaharu ^{[1
]}

Hiramoto, Toshiro ^{[1
]}

机构：

[1] Univ Tokyo, Inst Ind Sci, Meguro Ku, Tokyo 1538505, Japan

[2] Waseda Univ, Grad Sch Informat Prod & Syst, Kitakyushu, Fukuoka 8080135, Japan

来源：

JAPANESE JOURNAL OF APPLIED PHYSICS | 2017年 / 56卷 / 04期

关键词：

METAL-GATE TRANSISTORS; NONVOLATILE SRAM; LOGIC TECHNOLOGY; NOISE MARGIN;

D O I：

10.7567/JJAP.56.04CD03

中图分类号：

O59 [应用物理学];

学科分类号：

摘要：

The correlation between the static random access memory (SRAM) power-up state (i.e., state 0 or 1 immediately after the power supply is turned on) and cell transistor variation is systematically studied by circuit simulations and mismatch space partitioning. It is revealed that, while both the mismatches of pFETs (pull-up) and nFETs (pull-down and access) contribute, their relative importance changes depending on the voltage ramping speed. The static retention noise margin well correlates with the power-up state only if the ramping speed is sufficiently low. Otherwise, pull-up transistor mismatch dominates the power-up state determination owing to the interference of capacitive current and asymmetrical capacitive coupling of the storage nodes to the ground and power supply. (c) 2017 The Japan Society of Applied Physics

引用

页数：6

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