Design of 8T ROM Embedded SRAM using Double Wordline for Low Power High Speed Application

The speed of the processor mainly depends upon the propagation delay caused by memory accessing operation, because of having off chip ROM memory to store the look up tables or some other frequently used data. In complex DSP processors each and every operation has to access the off chip even though it has certain amount of on chip memory for random access purpose (RAM), but in all the time RAM will not be fully utilized for random access. The usage of that memory will depends upon the operation takes place in processor. So by adding an extra word line to change the random access memory to read only memory is proposed. Here 8T transmission gate based design is used to create an array 4X4 configurable random access memory and it has an extra word line to configure the certain part of RAM to ROM to act as cache memory. By using this on chip catch memory the propagation delay occurs while accessing off chip memory will be reduced, this will reduce the bottle neck to increase the speed of the processor. Due to extra word line separate address decoder logic was designed, decoder will decide which is to be consider as RAM and which is to be consider as ROM. Transmission gate based SRAM is used to avoid the weak logic occurred while using pass transistor logic.