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- [21] FPGA Implementation of a Pseudo-Random Signal Generator for RF Hardware Test and Evaluation 2020 IEEE 39TH INTERNATIONAL PERFORMANCE COMPUTING AND COMMUNICATIONS CONFERENCE (IPCCC), 2020,
- [23] Hardware Implementation of Template Matching Algorithm and its Performance Evaluation 2017 INTERNATIONAL CONFERENCE ON MICROELECTRONIC DEVICES, CIRCUITS AND SYSTEMS (ICMDCS), 2017,
- [24] Hardware Implementation and Performance Evaluation of DOCSIS 3.1 Upstream System 2020 IEEE INTERNATIONAL CONFERENCE ON CONSUMER ELECTRONICS - TAIWAN (ICCE-TAIWAN), 2020,
- [25] Hardware implementation and performance evaluation of complex binary adder designs 7TH WORLD MULTICONFERENCE ON SYSTEMICS, CYBERNETICS AND INFORMATICS, VOL II, PROCEEDINGS: COMPUTER SCIENCE AND ENGINEERING, 2003, : 68 - 73
- [26] Implementation of Double Arbiter PUF and Its Performance Evaluation on FPGA 2015 20TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), 2015, : 6 - 9
- [27] FPGA Implementation and Performance Evaluation of a Simultaneous Multithreaded Matrix Processor 2014 9TH INTERNATIONAL CONFERENCE ON COMPUTER ENGINEERING & SYSTEMS (ICCES), 2014, : 207 - 213
- [29] Real-time adaptive reduction of heart sounds from lung sound recordings using a new electronic stethoscope IEEE-EMBS ASIA PACIFIC CONFERENCE ON BIOMEDICAL ENGINEERING - PROCEEDINGS, PTS 1 & 2, 2000, : 800 - 801
- [30] The embedded digital stethoscope uses the adaptive noise cancellation filter and the Type I Chebyshev IIR bandpass filter to reduce the noise of the heart sound HEALTHCOM 2005: 7TH INTERNATIONAL WORKSHOP ON ENTERPRISE NETWORKING AND COMPUTING IN HEALTHCARE INDUSTRY, PROCEEDINGS, 2005, : 278 - 281