An 8-bit Bit-Slice TEA-Cryptographic Accelerator for 64-bit RSFQ Secure Coprocessors

被引：2

作者：

Yu, Pei-Shi ^{[1
,2
]}

Tang, Guang-Ming ^{[1
]}

Ye, Xiao-Chun ^{[1
]}

Fan, Dong-Rui ^{[1
]}

Zhang, Zhi-Min ^{[1
]}

Sun, Ning-Hui ^{[1
]}

机构：

[1] Chinese Acad Sci, Inst Comp Technol, State Key Lab Comp Architecture, Beijing, Peoples R China

[2] Univ Chinese Acad Sci, Beijing, Peoples R China

来源：

2019 IEEE INTERNATIONAL SUPERCONDUCTIVE ELECTRONICS CONFERENCE (ISEC) | 2019年

基金：

中国国家自然科学基金; 芬兰科学院;

关键词：

cryptographic accelerator; rapid single-flux-quantum (RSFQ); superconducting integrated circuits; FLUX-QUANTUM MICROPROCESSOR; DESIGN; IMPLEMENTATION;

D O I：

10.1109/isec46533.2019.8990902

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

An 8-bit bit-slice TEA-cryptographic accelerator for 64-bit RSFQ secure coprocessors is proposed. The accelerator is based on Tiny Encryption Algorithm (TEA) and mainly consists of bit-slice adders and bit-slice shifters. Synchronous concurrent-flow clocking is used to design a fully pipelined RSFQ logic design. For verifying the algorithm and the logic design, the RSFQ logic circuits of the proposed accelerator have been simulated with a target operating frequency of 50 GHz. It consists of 21 stages. The throughput is 7.672 x 10(7) 64-bit TEA encryptions per second.

引用

页数：4

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