An 8-bit Bit-Slice TEA-Cryptographic Accelerator for 64-bit RSFQ Secure Coprocessors

被引：2
|
作者：
Yu, Pei-Shi [1 ,2 ]
Tang, Guang-Ming [1 ]
Ye, Xiao-Chun [1 ]
Fan, Dong-Rui [1 ]
Zhang, Zhi-Min [1 ]
Sun, Ning-Hui [1 ]
机构：
[1] Chinese Acad Sci, Inst Comp Technol, State Key Lab Comp Architecture, Beijing, Peoples R China
[2] Univ Chinese Acad Sci, Beijing, Peoples R China
来源：
2019 IEEE INTERNATIONAL SUPERCONDUCTIVE ELECTRONICS CONFERENCE (ISEC) | 2019年
基金：
中国国家自然科学基金; 芬兰科学院;
关键词：
cryptographic accelerator; rapid single-flux-quantum (RSFQ); superconducting integrated circuits; FLUX-QUANTUM MICROPROCESSOR; DESIGN; IMPLEMENTATION;
D O I：
10.1109/isec46533.2019.8990902
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
An 8-bit bit-slice TEA-cryptographic accelerator for 64-bit RSFQ secure coprocessors is proposed. The accelerator is based on Tiny Encryption Algorithm (TEA) and mainly consists of bit-slice adders and bit-slice shifters. Synchronous concurrent-flow clocking is used to design a fully pipelined RSFQ logic design. For verifying the algorithm and the logic design, the RSFQ logic circuits of the proposed accelerator have been simulated with a target operating frequency of 50 GHz. It consists of 21 stages. The throughput is 7.672 x 10(7) 64-bit TEA encryptions per second.
引用
收藏
页数：4
相关论文
共 50 条
  • [41] A 12-ns 8-Mbyte DRAM secondary cache for 64-bit microprocessor
    不详
    [J]. NEC RESEARCH & DEVELOPMENT, 1999, 40 (02): : 266 - 266
  • [42] CNNET: A Configurable Hardware Accelerator for Efficient Inference of 8-bit Fixed-Point CNNs
    Agbalessi, Christie
    Indovina, Mark A.
    [J]. 2023 IEEE 36TH INTERNATIONAL SYSTEM-ON-CHIP CONFERENCE, SOCC, 2023, : 196 - 201
  • [43] The GNU 64-bit PL8 compiler: Toward an open standard environment for firmware development
    Gellerich, Wolfgang
    Hendel, Torsten
    Land, Rudolf
    Lehmann, Helge
    Mueller, Michael
    Oden, Peter H.
    Penner, Hartmut
    [J]. 1600, IBM Corporation (48): : 3 - 4
  • [44] NUMA-Aware DGEMM Based on 64-Bit ARMv8 Multicore Processors Architecture
    Zhang, Wei
    Jiang, Zihao
    Chen, Zhiguang
    Xiao, Nong
    Ou, Yang
    [J]. ELECTRONICS, 2021, 10 (16)
  • [45] AN 8-BIT SLICE GAAS BUS LOGIC LSI FOR A HIGH-SPEED PARALLEL PROCESSING SYSTEM
    KAMEYAMA, A
    KAWAKYU, K
    SASAKI, T
    SESHITA, T
    TERADA, T
    KITAURA, Y
    TOYODA, N
    MAEDA, A
    [J]. GAAS IC SYMPOSIUM /: TECHNICAL DIGEST 1989, 1989, : 105 - 108
  • [46] The GNU 64-bit PL8 compiler: Toward an open standard environment for firmware development
    Gellerich, W
    Hendel, T
    Land, R
    Lehmann, H
    Mueller, M
    Oden, PH
    Penner, H
    [J]. IBM JOURNAL OF RESEARCH AND DEVELOPMENT, 2004, 48 (3-4) : 543 - 556
  • [47] 8-Bit Asynchronous Sparse-Tree Superconductor RSFQ Arithmetic-Logic Unit With a Rich Set of Operations
    Dorojevets, Mikhail
    Ayala, Christopher L.
    Yoshikawa, Nobuyuki
    Fujimaki, Akira
    [J]. IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, 2013, 23 (03)
  • [48] CHIP SET EASES BIT-SLICE DESIGN WHILE TACKLING VIDEO-SPEED PROCESSING .1. MULTIPLE INTERNAL BUSES SPEED 8-BIT-WIDE SLICES
    NIEHAUS, J
    DUVAL, J
    ENGLADE, J
    [J]. ELECTRONICS, 1983, 56 (21): : 133 - 135
  • [49] Implementation of an Accurate and Efficient Compensated DGEMM for 64-bit ARMv8 Multi-Core Processors
    Jiang, Hao
    Wang, Feng
    Li, Kuan
    Yang, Canqun
    Zhao, Kejia
    Huang, Chun
    [J]. 2015 IEEE 21ST INTERNATIONAL CONFERENCE ON PARALLEL AND DISTRIBUTED SYSTEMS (ICPADS), 2015, : 491 - 498
  • [50] Design and Implementation of a Highly Efficient DGEMM for 64-bit ARMv8 Multi-Core Processors
    Wang, Feng
    Jiang, Hao
    Zuo, Ke
    Su, Xing
    Xue, Jingling
    Yang, Canqun
    [J]. 2015 44TH INTERNATIONAL CONFERENCE ON PARALLEL PROCESSING (ICPP), 2015, : 200 - 209
12345