A Low-Power Low-Phase-Noise CMOS VCO using RF SiP Technology

被引：0

作者：

Ohashi, Kazuma ^{[1
]}

Ito, Yusaku ^{[1
]}

Ito, Hiroyuki ^{[2
]}

Okada, Kenichi ^{[1
]}

Hatakeyama, Hideki ^{[3
]}

Ozawa, Naoyuki ^{[3
]}

Sato, Masakazu ^{[3
]}

Aizawa, Takuya ^{[3
]}

Ito, Tatsuya ^{[3
]}

Yamauchi, Ryozo ^{[4
]}

Masu, Kazuya ^{[1
]}

机构：

[1] Tokyo Inst Technol, Integrated Res Inst, Midori Ku, 4259-R2-17 Nagatsuta, Yokohama, Kanagawa 2268503, Japan

[2] Tokyo Inst Technol, Precis & Intelligent Lab, Midori Ku, 4259-R2-17 Nagatsuta, Yokohama, Kanagawa 2268503, Japan

[3] Fujikura Ltd, Elect Device Lab, Chiba 2858550, Japan

[4] Fujikura Ltd, Chiba 1358512, Japan

来源：

2007 ASIA PACIFIC MICROWAVE CONFERENCE, VOLS 1-5 | 2007年

关键词：

RF SiP technology; high-Q inductor; LC-VCO; low power; low phase noise; CMOS;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a feasibility study on VCO using RF SiP technology, which is an RF application of stacked SiP, An off-chip inductor is implemented in a separated chip, and measured Q factor is 130. A phase noise is -119 dBc/Hz at 1 MHz offset for a 5.84-GHz carrier frequency, and frequency tuning range is 5.73 GHz-5.95 GHz. Power consumption is 1.93 mW, and 180 nm CMOS process is utilized. FOM is -192 dBc/Hz.

引用

下载

页码：1963 / +

页数：2

共 50 条

[41] A low-power, low phase noise CMOS VCO with suppression of 1/f flicker noise up-conversion
Oh, Nam-Jin
Heo, Deuk
IEICE ELECTRONICS EXPRESS, 2012, 9 (24): : 1881 - 1886
[42] Design of low-noise, low-power 10-GHz VCO using 0.18-μm CMOS technology
Ohhata, K
Harasawa, K
Honda, M
Yamashita, K
IEICE TRANSACTIONS ON ELECTRONICS, 2006, E89C (02) : 203 - 205
[43] A low phase noise quadrature LC VCO in CMOS technology
Sze, BY
Ho, CL
2005 IEEE RADIO FREQUENCY INTEGRATED CIRCUITS (RFIC) SYMPOSIUM, DIGEST OF PAPERS, 2005, : 649 - 652
[44] A 1.8-GHz low-phase-noise CMOS VCO using optimized hollow spiral inductors
Craninckx, J
Steyaert, MSJ
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1997, 32 (05) : 736 - 744
[45] A10-GHz 0.88-mW Low-Phase-Noise CMOS VCO
Syu, Jin-Rong
Lin, Zhi-Ming
2009 52ND IEEE INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1 AND 2, 2009, : 1063 - 1066
[46] A 1.8-GHz low-phase-noise spiral-LC CMOS VCO
Craninckx, J
Steyaert, M
1996 SYMPOSIUM ON VLSI CIRCUITS - DIGEST OF TECHNICAL PAPERS, 1996, : 30 - 31
[47] A low-phase-noise low-power 27-GHz SiGe-VCO using merged-transformer matching circuit technique
Nakamura, Takahiro
Masuda, Toru
Washio, Katsuyoshi
Kondoh, Hiroshi
2007 IEEE RADIO FREQUENCY INTEGRATED CIRCUITS (RFIC) SYMPOSIUM, DIGEST OF PAPERS, 2007, : 413 - +
[48] A LOW-PHASE-NOISE CMOS QUADRATURE VCO WITH PMOS BACK-GATE COUPLING
Yeh, Mel-Ling
Lin, Yao-Chian
Liou, Wan-Rone
Kuo, Sheng-Hing
Roblin, Patrick
Chang, Chung Cheng
MICROWAVE AND OPTICAL TECHNOLOGY LETTERS, 2010, 52 (12) : 2682 - 2685
[49] Low-phase-noise CMOS VCO with new drain-gate feedback path
Rezaei, Marzieh
Jannesari, Abumoslem
ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 2016, 88 (01) : 89 - 95
[50] Alow-phase-noise and low-power CMOS colpitts VCO using Gmboosting and capacitance switching techniques
Pakasiri, Chatrpol
You, Jia-Hao
Wang, Sen
MICROWAVE AND OPTICAL TECHNOLOGY LETTERS, 2021, 63 (01) : 46 - 50

← 1 2 3 4 5 →