Performance Analysis of Modified SHA-3

被引:6
|
作者
Chandran, Nithin R. [1 ]
Manuel, Ebin M. [1 ]
机构
[1] Govt Engn Coll, Idukki, India
关键词
Cryptography; Secure Hash Algorithm-3; FPGA; Area reduction;
D O I
10.1016/j.protcy.2016.05.168
中图分类号
TP39 [计算机的应用];
学科分类号
081203 ; 0835 ;
摘要
Security services have become an inseparable feature of almost all digital transactions. A crucial module of these scheme isintegrity, which is performed using a cryptographic hash function. Secure Hash Algorithm can be an efficient hashing technique. SHA-3 is the most recent and efficient Secure Hash Algorithm. Keccak has been chosen as the official algorithm for SHA-3 in2012. In this paper we propose a modification on the design of Secure Hash Algorithm (SHA-3) on Xilinx Field ProgrammableGate Array (FPGA) device. In order to provide reliable architecture for this algorithm, a concurrent error tolerant scheme forSHA-3 is used. A system based on the combination of SHA-3 and error tolerant scheme is also described. Simulation resultsshows, an efficiency in area and delay of SHA-3 designs. (C) 2016 The Authors. Published by Elsevier Ltd.
引用
收藏
页码:904 / 910
页数:7
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