Design and Implementation of Configurable FFT/IFFT Soft-Core Based on FPGA

As a basic transforming operation between time field and frequency field, FFT has been widely used in detection, telecommunication, signal processing, multimedia communication etc. The implementation of the FFT algorithms on FPGA is always the hot research spots. In order to overcome the shortcomings on the FPGA resource reusability used in FFT algorithm, this article discusses a new configurable and high efficient FFT/IFFT soft-core solution. The FFT/IFFT soft-core adopts radix-2(2) algorithm and Single-Path Delay Feedback (SDF) pipeline structure. Its configurable factors include: FFT/IFFT, FFT points (2(n), n is an element of [3,12]), fixed-point bit width, clock delay of complex multiplier. The design takes FPGA chip Stratix II EP2S130F780C4 as hardware platform, and the complete simulation and synthesis is taken. The maximum operating frequency is up to 306.30MHz. If 300MHz clock frequency used, 4096-point FFT could be realized in 26.73us, and the consumption of memory resources is only 148Kbit. Compared with Altera FFT IP-core, our FFT/IFFT soft-core has a little bit longer computing time (0.6%). However, the LE resource consumption is only 79% of Altera FFT IP-core.