An on-chip BP learning neural network with ideal neuron characteristics and learning rate adaptation

被引:15
|
作者
Lu, C [1 ]
Shi, BX [1 ]
Chen, L [1 ]
机构
[1] Tsinghua Univ, Inst Microelect, Beijing 100084, Peoples R China
基金
中国国家自然科学基金;
关键词
circuit design; hardware implementation; neural network; on-chip BP learning;
D O I
10.1023/A:1014476806076
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
An on-chip BP(Back-Propagation) learning neural network with ideal neuron characteristics and learning rate adaptation is designed. A prototype LSI has been fabricated with a 1.2 mum CMOS double-poly double-metal technology. A novel neuron circuit with ideal characteristics and programmable parameters is proposed. It can generate not only the sigmoid function but also its derivative. The test results of this neuron circuit show that both functions match with their ideal values very accurately. A learning rate adaptation circuit is also presented to accelerate the convergence speed. The 2-D binary classification and \sin(x) function fitness experiments are done to the chip. Both experiments verify the superior performance of this BP neural network with on-chip learning.
引用
收藏
页码:55 / 62
页数:8
相关论文
共 50 条
  • [31] On-chip learning in pulsed silicon neural networks
    Lehmann, T
    Woodburn, R
    Murray, AF
    [J]. ISCAS '97 - PROCEEDINGS OF 1997 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS I - IV: CIRCUITS AND SYSTEMS IN THE INFORMATION AGE, 1997, : 693 - 696
  • [32] On-chip learning for a scalable hybrid neural architecture
    Alhalabi, BA
    Bayoumi, MA
    [J]. ISCAS '97 - PROCEEDINGS OF 1997 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS I - IV: CIRCUITS AND SYSTEMS IN THE INFORMATION AGE, 1997, : 677 - 680
  • [33] Efficient rate adjustment hardware for on-chip learning
    Rezaie, MG
    Farbiz, F
    Behnam, A
    [J]. ICCDCS 2004: Fifth International Caracas Conference on Devices, Circuits and Systems, 2004, : 98 - 102
  • [34] The CMOS design of robust neural chip with the on-chip learning capability
    Wu, CY
    Liu, RY
    Jou, IC
    ShyhJYE, FJ
    [J]. ISCAS 96: 1996 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS - CIRCUITS AND SYSTEMS CONNECTING THE WORLD, VOL 3, 1996, : 426 - 429
  • [35] An experimental analog VLSI neural network with on-chip Back-Propagation learning
    Valle, M
    Caviglia, DD
    Bisio, GM
    [J]. ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 1996, 9 (03) : 231 - 245
  • [36] Pulse-width-modulation feedforward neural network design with on-chip learning
    Bor, JC
    Wu, CY
    [J]. APCCAS '96 - IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS '96, 1996, : 369 - 372
  • [37] On-chip Learning In A Conventional Silicon MOSFET Based Analog Hardware Neural Network
    Dey, Nilabjo
    Sharda, Janak
    Saxena, Utkarsh
    Kaushik, Divya
    Singh, Utkarsh
    Bhowmik, Debanjan
    [J]. 2019 IEEE BIOMEDICAL CIRCUITS AND SYSTEMS CONFERENCE (BIOCAS 2019), 2019,
  • [38] Pulse mode multilayer neural network with floating point operation and on-chip learning
    Hikawa, H
    [J]. IJCNN 2000: PROCEEDINGS OF THE IEEE-INNS-ENNS INTERNATIONAL JOINT CONFERENCE ON NEURAL NETWORKS, VOL II, 2000, : 71 - 76
  • [39] Toward a general-purpose analog VLSI neural network with on-chip learning
    Montalvo, AJ
    Gyurcsik, RS
    Paulos, JJ
    [J]. IEEE TRANSACTIONS ON NEURAL NETWORKS, 1997, 8 (02): : 413 - 423
  • [40] A Sparse Coding Neural Network ASIC With On-Chip Learning for Feature Extraction and Encoding
    Knag, Phil
    Kim, Jung Kuk
    Chen, Thomas
    Zhang, Zhengya
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2015, 50 (04) : 1070 - 1079