5 GHz 0.25-μm CMOS static frequency divider

被引：0

作者：

Ding, Jingfeng ^{[1
]}

Wang, Zhigong ^{[1
]}

Qiu, Yinghua ^{[1
]}

Wang, Gui ^{[1
]}

Zhu, En ^{[1
]}

机构：

[1] SW Univ, Inst RF & OC ICs, Nanjing 210096, Peoples R China

来源：

2005 ASIA-PACIFIC MICROWAVE CONFERENCE PROCEEDINGS, VOLS 1-5 | 2005年

关键词：

frequency divider; latch; CMOS; jitter;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 5 GHz 2:1 static frequency divider IC was realized in a 0.25-mu m mixed-signal CMOS technology with an f(r) of 18.6 GHz. The divider is based on a Master-slave Toggle Flip-Flop (MSTFF) of Source Coupled FET Logic (SCFL) and a wide band output buffer. The basic circuits and layout strategies to achieve low jitter and high speed are discussed. The measured rms jitter of the output waveform is 1.38 ps at 5 GHz input. The core power dissipation is 5 mW under a 2.5V supply.

引用

页码：1047 / 1049

页数：3

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