The challenges and opportunities in GHz microprocessor design on 0.13μm and beyond technologies

CMOS technology scaling continues to be the main driving force behind the advancement of high-performance microprocessors. As the feature size of CMOS transistor shrinks below 0.13 mum, and gate delay is rapidly reduced below 20ps, the frequency of leading edge microprocessors has well exceeded 1Ghz barrier now. The combination of both transistor and frequency scaling has created many new challenges in the high-speed CPU design. This paper will address many of the key technical challenges in today's multi-GHz CPU design, including low-power and low-leakage design, high-speed and skew tolerant latching strategy, on-die high-speed cache, and robust design against soft-error. The potential design solutions arc discussed.