Jitter impact on clock distribution in LHC experiments

被引:7
|
作者
Baron, S. [1 ]
Mastoridis, T. [1 ]
Troska, J. [1 ]
Baudrenghien, P. [1 ]
机构
[1] CERN, CH-1211 Geneva 23, Switzerland
来源
关键词
Beam dynamics; Front-end electronics for detector readout; Detector control systems (detector and experiment monitoring and slow-control systems; architecture; hardware; algorithms; databases); Digital electronic circuits;
D O I
10.1088/1748-0221/7/12/C12023
中图分类号
TH7 [仪器、仪表];
学科分类号
0804 ; 080401 ; 081102 ;
摘要
The LHC Bunch Clock is one of the most important accelerator signals delivered to the experiments. Being directly derived from the Radio Frequency driving the beams in the accelerator by a simple division of its frequency by a factor of 10, the Bunch Clock signal represents the frequency at which the bunches are crossing each other at each experiment. It is thus used to synchronize all the electronics systems in charge of event detection. Its frequency is around 40.079 MHz, but varies with beam parameters (energy, particle type, etc) by a few hundreds of Hz. The present paper discusses the quality of this Bunch Clock signal in terms of jitter. It is in particular compared to typical requirements of electronic components of the LHC detectors and put in perspective with the intrinsic jitter of the beam itself, to which this signal is related.
引用
收藏
页数:12
相关论文
共 50 条
  • [31] Clock Distribution and Readout Architecture for the ATLAS Tile Calorimeter at the HL-LHC
    Carrio, F.
    Valero, A.
    IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2019, 66 (07) : 1014 - 1020
  • [32] The ticking of the biological clock - impact on animal experiments and pharmacology
    Lemmer, B.
    JOURNAL OF VETERINARY PHARMACOLOGY AND THERAPEUTICS, 2009, 32 : 5 - 7
  • [33] Jitter suppressed on-chip clock distribution using package plane cavity resonance
    Lee, Woojin
    Ryu, Chunghyun
    Park, Jongbae
    Kim, Joungho
    2008 ASIA-PACIFIC SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY AND 19TH INTERNATIONAL ZURICH SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY, VOLS 1 AND 2, 2008, : 427 - 430
  • [34] A Low-jitter Phase-locked Resonant Clock Generation and Distribution Scheme
    Mandal, Ayan
    Bollapalli, Kalyana C.
    Jayakumar, Nikhil
    Khatri, Sunil P.
    Mahaptra, Rabi N.
    2013 IEEE 31ST INTERNATIONAL CONFERENCE ON COMPUTER DESIGN (ICCD), 2013, : 487 - 490
  • [35] Implementation of low jitter clock distribution using chip-package hybrid interconnection
    Ryu, C
    Chung, D
    Bae, K
    Yu, J
    Kim, J
    ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING, 2004, : 291 - 294
  • [36] A Low-Jitter Synchronous Clock Distribution Scheme Using a DAC Based PLL
    Wu, Jie
    Ma, Yichao
    Zhang, Jie
    Xie, Mingpu
    IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2010, 57 (02) : 589 - 594
  • [37] MINIMIZING JITTER IN CLOCK EXTRACTION CIRCUITS
    FOSTER, B
    ELECTRONIC ENGINEERING, 1987, 59 (723): : 45 - &
  • [38] A jitter suppression technique for a clock multiplier
    Ishii, K
    Kishine, K
    Ichino, H
    IEICE TRANSACTIONS ON ELECTRONICS, 2000, E83C (04): : 647 - 651
  • [39] The effect of clock jitter on the DR of ΣΔ modulators
    van Veldhoven, Robert
    Nuijten, Peter
    van Zeijl, Paul
    2006 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11, PROCEEDINGS, 2006, : 2009 - +
  • [40] Clock Jitter Effects on Sampling: A Tutorial
    Azeredo-Leme, Carlos
    IEEE CIRCUITS AND SYSTEMS MAGAZINE, 2011, 11 (03) : 26 - 37