A 96-dB CMOS Programmable Gain Amplifier for Low-IF GPS Receiver

A programmable gain amplifier (PGA) was designed for a Low-IF GPS receiver. Linearity method which was based on the differential degeneration and gm boost structure was used in the circuit. Transistors which were working in the sub-threshold region were applied in the built-in DC-Offset correction circuit. This PGA provided a 96-dB digitally controlled gain range with a step of 6-dB, and the overall gain accuracy was 0.03dB. The 3dB bandwidth of the PGA was 300MHz. The noise figure at the maximum gain was 23.7dB. The IIP3 was -5dBm for the minimum gain. The PGA was implemented in a 0.18um CMOS process and approximately occupied 0.097mm2. This PGA consumed 3.5mA at a 1.8V supply.