Non-planar substrate effect on the interface trap capacitance of metal-oxide-semiconductor structures with ultra thin oxides

被引:6
|
作者
Tseng, Po-Hao [1 ]
Hwu, Jenn-Gwo [1 ]
机构
[1] Natl Taiwan Univ, Grad Inst Elect Engn, Dept Elect Engn, Taipei 10617, Taiwan
关键词
ELECTRICAL CHARACTERISTICS; THERMAL-OXIDATION; TUNNELING CURRENT; SILICON; THICKNESS;
D O I
10.1063/1.4761972
中图分类号
O59 [应用物理学];
学科分类号
摘要
Redistribution of interface trap capacitance (Cit) was observed in non-planar substrate metal-oxide-semiconductor (MOS) capacitors with ultra thin oxides. It was found that the behavior of Cit of non-planar substrate MOS capacitors is dependent on the non-planar portion. The non-planar devices exhibit two peaks distribution in Cit due to multiple surfaces effect. A Cit model combining uniform and non-uniform areas effect was proposed for the observation. The non-uniform substrate MOS capacitors exhibit significant non-uniform deep depletion behaviors and degradation in constant voltage stress reliability. (C) 2012 American Institute of Physics. [http://dx.doi.org/10.1063/1.4761972]
引用
收藏
页数:7
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