Simultaneous Reconfiguration of Issue-width and Instruction Cache for a VLIW Processor

This paper presents an analysis on the impact of simultaneous instruction cache (I-cache) and issue-width reconfiguration for a very long instruction word (VLIW) processor. The issue-width of the processor can be adjusted at run-time to be 2-issue, 4-issue, or 8-issue, and the I-cache can be reconfigured in terms of associativity, cache size, and line size. We observe that, compared to reconfiguring only the I-cache for a fixed issue-width core, reconfiguring the issue-width and I-cache together can further reduce the execution time, energy consumption, and/or the energy-delay product (EDP). The results for the MiBench and the PowerStone benchmark suites show that compared to "2-issue + the best I-cache", "4-issue + the best I-cache" can reduce execution time, energy consumption, and EDP by up to 37%, 11%, and 36%, respectively, for different applications. Similarly, compared to "2-issue + the best I-cache", "8-issue + the best I-cache" can reduce execution time and EDP by up to 46% and 30%, respectively, for different applications.