共 50 条
- [1] Design and Implementation of an Energy Efficient Dual-Issue Processor Beijing Daxue Xuebao (Ziran Kexue Ban)/Acta Scientiarum Naturalium Universitatis Pekinensis, 2023, 59 (04): : 555 - 562
- [2] Design of Instruction Decode Logic for Dual-issue Superscalar Processor Based on LEON2 2013 IEEE THIRD INTERNATIONAL CONFERENCE ON CONSUMER ELECTRONICS - BERLIN (ICCE-BERLIN), 2013,
- [3] Design and Implementation of Multi-Thread Interaction Based on Android PROCEEDINGS OF THE INTERNATIONAL CONFERENCE ON MANAGEMENT AND ENGINEERING (CME 2014), 2014, : 11 - 18
- [4] Design and Realization of Multi-Thread Structure for an LLRP Server APPLIED MATHEMATICS & INFORMATION SCIENCES, 2012, 6 (03): : 1117 - 1123
- [5] Energy Efficient Dual-Issue Processor for Embedded Applications 2015 IEEE 12TH INTERNATIONAL CONFERENCE ON NETWORKING, SENSING AND CONTROL (ICNSC), 2015, : 544 - 549
- [7] A multi-thread processor architecture based on the continuation model INNOVATIVE ARCHITECTURE FOR FUTURE GENERATION HIGH-PERFORMANCE PROCESSORS AND SYSTEMS, 2005, : 83 - 90
- [8] Multithreading and Interprocessor Communication in a Dual-Issue Pipelined Processor 2008 JOINT IEEE NORTH-EAST WORKSHOP ON CIRCUITS AND SYSTEMS AND TAISA CONFERENCE, 2008, : 33 - 36
- [9] Design of a 32-Bit RISC processor with dual-issue and dual-pipeline architecture Xibei Gongye Daxue Xuebao/Journal of Northwestern Polytechnical University, 2011, 29 (01): : 6 - 11
- [10] Multi-thread VLIW processor architecture for HDTV decoding PROCEEDINGS OF THE IEEE 2000 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 2000, : 559 - 562