Hybrid ADC based on Flash and Delay-Line Structures

被引：0
|
作者：
Qin, Lin [1 ]
Zhao, Menglian [1 ]
Wu, Xiaobo [1 ]
Shen, Xuzhen [1 ]
机构：
[1] Zhejiang Univ, Inst VLSI Design, Hangzhou 310027, Zhejiang, Peoples R China
来源：
FIFTH INTERNATIONAL CONFERENCE ON MACHINE VISION (ICMV 2012): ALGORITHMS, PATTERN RECOGNITION AND BASIC TECHNOLOGIES | 2013年 / 8784卷
关键词：
Hybrid ADC; flash ADC; delay line; analog delay locked loop (ADLL);
D O I：
10.1117/12.2014038
中图分类号：
TP18 [人工智能理论];
学科分类号：
081104 ; 0812 ; 0835 ; 1405 ;
摘要：
A pseudo 9-bit 10 MSample/s hybrid Analog to Digital Converter ( ADC) is proposed for applying to digital power controller. It features its structure that consists of three 3-bit ADCs: a flash ADC and two delay-line based window ADCs. The first one works in the entire voltage range. And the other two only work in the desired voltage window to improve the resolution. The ADC is designed and simulated in TSMC 0.35-mu m mixed signal process. Simulation results show that the expected funtions are achieved.
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页数：6
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