Ge0.97Sn0.03 p-channel metal-oxide-semiconductor field-effect transistors: Impact of Si surface passivation layer thickness and post metal annealing

A low-temperature (similar to 370 degrees C) Si2H6 treatment was used to form an ultrathin Si layer on a Ge0.97Sn0.03 channel layer on Ge substrate in the fabrication of Ge0.97Sn0.03 channel pMOSFETs. The impact of the Si passivation layer thickness on the electrical characteristics of Ge0.97Sn0.03 pMOSFETs was investigated. By increasing the thickness of Si passivation layer from 4 to 7 monolayers (ML), the effective hole mobility mu(eff) at an inversion carrier density N-inv of 1 x 10(13) cm(-2) was improved by similar to 19% +/- 64%. This is attributed to reduced carrier scattering by charges found at the interface between the Si layer and the gate dielectric. In addition, the effects of post metal annealing (PMA) were investigated. It was observed that the mid-gap interface trap density D-it was reduced in devices with PMA. Ge0.97Sn0.03 pMOSFETs with PMA have improved intrinsic transconductance G(m,int), subthreshold swing S, and mu(eff) as compared to the control devices without PMA. (C) 2013 AIP Publishing LLC.