Efficient systolic modular multiplier/squarer for fast exponentiation over GF(2m)

被引：23

作者：

Choi, Se-Hyu ^{[1
]}

Lee, Keon-Jik ^{[1
]}

机构：

[1] Kyungpook Natl Univ, Sch Architectural Civil Environm & Energy Engn, Daegu 702701, South Korea

来源：

IEICE ELECTRONICS EXPRESS | 2015年 / 12卷 / 11期

关键词：

modular multiplication; finite field arithmetic; systolic array; FINITE-FIELDS GF(2M);

D O I：

10.1587/elex.12.20150222

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Using the concept of common components, this letter shows that field multiplication and squaring over GF(2(m)) can be efficiently combined, with little hardware overhead. The analysis results show that about 39.23% area-time (AT) complexity is improved when we employ the combined systolic multiplier/squarer instead of implementing the multiplier and the squarer separately in the least significant bit (LSB)-first exponentiation. The proposed architecture features regularity, unidirectional data flow, and local interconnection, and thus is well suited to VLSI implementation.

引用

下载

页数：6

共 50 条

[31] Pipelined systolic multiplier for finite fields GF(2m)
Kim, HS
Yoo, KY
Kim, JJ
Kim, TG
INTERNATIONAL CONFERENCE ON PARALLEL AND DISTRIBUTED PROCESSING TECHNIQUES AND APPLICATIONS, VOLS I-V, PROCEEDINGS, 1999, : 1224 - 1229
[32] Efficient digit-serial systolic multiplier for finite fields GF(2m)
Kim, KW
Lee, KJ
Yoo, KY
COMPUTER APPLICATIONS IN INDUSTRY AND ENGINEERING, 2001, : 205 - 208
[33] A Hardware Pipelined Architecture of a Scalable Montgomery Modular Multiplier over GF(2m)
Reymond, Guillaume
Murillo, Victor
2013 INTERNATIONAL CONFERENCE ON RECONFIGURABLE COMPUTING AND FPGAS (RECONFIG), 2013,
[34] Efficient Scalable Serial Multiplier Over GF(2m) Based on Trinomial
Gebali, Fayez
Ibrahim, Atef
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2015, 23 (10) : 2322 - 2326
[35] FPGA implementation of an efficient multiplier over finite fields GF(2m)
García-Martínez, MA
Posada-Gómez, R
Morales-Luna, G
Rodríguez-Henríquez, F
2005 INTERNATIONAL CONFERENCE ON RECONFIGURABLE COMPUTING AND FPGAS (RECONFIG 2005), 2005, : 171 - 175
[36] Efficient GF(2m) squarer for Type C.2 pentanomial
Chen, Qing
Li, Yin
Qi, Chuanda
ELECTRONICS LETTERS, 2018, 54 (13) : 829 - +
[37] A systolic multiplier with LSB first algorithm over GF(2m) which is as efficient as the one with MSB first algorithm
Kwon, S
Kim, CH
Hong, CP
PROCEEDINGS OF THE 2003 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL V: BIO-MEDICAL CIRCUITS & SYSTEMS, VLSI SYSTEMS & APPLICATIONS, NEURAL NETWORKS & SYSTEMS, 2003, : 633 - 636
[38] Partitioned systolic architecture for modular multiplication in GF(2m)
Kim, HS
Lee, SW
Yoo, KY
INFORMATION PROCESSING LETTERS, 2000, 76 (03) : 135 - 139
[39] High-throughput area-delay-efficient systolic multiplier over GF(2m) for a class of trinomials
Pillutla, Siva Ramakrishna
Boppana, Lakshmi
MICROPROCESSORS AND MICROSYSTEMS, 2020, 77
[40] Modular Inversion Architecture over GF(2m) Using Optimal Exponentiation Blocks for ECC Cryptosystems
Zhang, Jingqi
Jiang, Yujie
Wang, An
2024 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, ISCAS 2024, 2024,

← 1 2 3 4 5 →