Implementing Dynamic Reconfigurable CNN-based Full-Adder

被引:0
|
作者
Liu, Yanyi [1 ,2 ]
Liu, Wenbo [1 ]
Yuan, Xiaozheng [1 ]
Chen, Guanrong [3 ]
机构
[1] Nanjing Univ Aeronaut & Astronaut, Dept Automat, Nanjing, Jiangsu, Peoples R China
[2] Nnajing Forestry Univ, Coll Informat Sci & Technol, Nanjing, Jiangsu, Peoples R China
[3] City Univ Hong Kong, Dept Elect Engn, Hong Kong, Hong Kong, Peoples R China
关键词
CELLULAR NEURAL-NETWORKS; LOGIC; AUTOMATA;
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
This paper presents a new approach to implement the dynamic reconfigurable logical systems based on Cellular Neural Networks (CNN), comparing with utilizing the chaos computing system, which is easier to implement in engineering applications and more stable. We provided and experimentally demonstrated the basic principle for obtaining a full-adder by using uncoupled CNN cells. The actual circuit to implementing the full-adder and transforming from adder to subtractor also has been presented.
引用
收藏
页数:5
相关论文
共 50 条
  • [31] A novel lightweight CNN-based error-reduced carry prediction approximate full adder design for multimedia applications
    Nishanth, R.
    Sulochana, C. Helen
    NEURAL COMPUTING & APPLICATIONS, 2024, 36 (12): : 6421 - 6440
  • [32] A novel lightweight CNN-based error-reduced carry prediction approximate full adder design for multimedia applications
    R. Nishanth
    C. Helen Sulochana
    Neural Computing and Applications, 2024, 36 : 6421 - 6440
  • [33] High-Reliability, Reconfigurable, and Fully Non-volatile Full-Adder Based on SOT-MTJ for Image Processing Applications
    Jin, Xing
    Chen, Weichong
    Li, Ximing
    Yin, Ningyuan
    Wan, Caihua
    Zhao, Mingkun
    Han, Xiufeng
    Yu, Zhiyi
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2023, 70 (02) : 781 - 785
  • [34] Electro-optical full-adder/full-subtractor based on graphene-silicon switches
    Zivarian, Hossein
    Zarifkar, Abbas
    Miri, Mehdi
    JOURNAL OF NANOPHOTONICS, 2018, 12 (01)
  • [35] QUATERNARY THRESHOLD LOGIC FULL-ADDER CIRCUIT WITH COMPLEMENTARY INPUTS
    WHEATON, LB
    CURRENT, KW
    INTERNATIONAL JOURNAL OF ELECTRONICS, 1984, 56 (04) : 539 - 545
  • [36] Low-power logic styles for full-adder circuits
    Quintana, JM
    Avedillo, MJ
    Jiménez, R
    Rodríguez-Villegas, E
    ICECS 2001: 8TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS I-III, CONFERENCE PROCEEDINGS, 2001, : 1417 - 1420
  • [37] A molecular full-adder and full-subtractor, an additional step toward a moleculator
    Margulies, D
    Melman, G
    Shanzer, A
    JOURNAL OF THE AMERICAN CHEMICAL SOCIETY, 2006, 128 (14) : 4865 - 4871
  • [38] A Radiation-Hardened CMOS Full-Adder Based on Layout Selective Transistor Duplication
    Azimi, Sarah
    De Sio, Corrado
    Sterpone, Luca
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2021, 29 (08) : 1596 - 1600
  • [39] Flexible processor based on full-adder/D-flip-flop merged module
    Sakaidani, S
    Miyamoto, N
    Ohmi, T
    PROCEEDINGS OF THE ASP-DAC 2001: ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 2001, 2001, : 35 - 36
  • [40] Low Power and Fully Nonvolatile Full-Adder Based on STT-SHE-MRAM
    Adelkhani, Morteza
    Aminian, Mahdi
    SPIN, 2023, 13 (03)