A V-band Low Noise Amplifier with 18.1 dB Gain and 6.3 dB NF in 90-nm CMOS Process Technology

A three-stage low noise amplifier (LNA) implemented in the TSMC 90-nm CMOS process technology for V-band applications is proposed in this paper. The proposed low noise amplifier consists of three commonsource stages with inductive degeneration. We use microstrip lines for input/output matching and as loads for all stages. The chip size of the proposed low noise amplifier is 0.608 x 0.636 mm(2). The measured peak gain is 18.1 dB at 59.9 GHz with 3 dB bandwidth from 58 to 62.4 GHz. The lowest measured noise figure (NF) is 6.3 dB at 61 GHz and 63.5 GHz, respectively, and NF is from 6.3 dB to 8dB for the 57-64 GHz frequency range. The measured input 1 dB compression point (P1 dB) is -19 dBm and input third intercept point (IIP3) is -10 dBm. The proposed circuit draws a 32.6 mW dc-power from a 1.2-V supply.