FPGA implementation of cellular automata spaces using a CAM based cellular architecture

This paper presents a content addressable memory (CAM) based architecture for implementing cellular automata (CA) spaces within afield programmable gate array (FPGA). CAMs have proved useful for implementing a number of applications that involve the need to match input data to stored data. This ability is a necessity when implementing cellular automata transition rule sets within hardware. A CAM matching process allows the next state of all cells in an automata space to be found efficiently in as little as a single clock cycle without the need for a complex memory searching algorithm. FPGAs are useful for creating cellular architectures as they are reconfigurable making it possible to model fault tolerance. Research into cellular architectures which can be made fault tolerant is of importance in the current era as faults are becoming increasingly common due to decreasing device dimensions and the increasing complexity of chips and the designs being implemented with them. The cells within the CAM architecture on the FPGA can be configured in different ways allowing it to adapt to varying system requirements and design density. This flexibility allows important factors such as look up table (LUT) usage and clock cycles per time step to be optimised during the design process.