Implementation of a High Speed Low power DSP Co-Processor based on Clock gating and Vedic Mathematics

This paper presents a computational technique called "Vedic Mathematics" coupled with clock gating for designing a DSP co-processor that is fast as compared to other processors having conventional multiplier designs. A processor's speed is essentially determined by the speed of its multiplier and MAC blocks. In this paper we have designed a high-speed 16x16 bit multiplier. This architecture employs the process of vertical and crossed multiplication of the multiplier and multiplicand. The code for the proposed Vedic multiplier is written in Verilog HDL language followed by synthesis using EDA tool, Xilinx ISE 14.3. Finally, a comparison is made between Vedic and booth multiplier. As expected, the performance of proposed design is found slightly better in terms of area (FPGA resources). The delay analysis of Vedic versus Booth multiplier shows that Vedic method provides for faster execution speeds[1].