ADC Testing With Verification

被引:7
|
作者
Fodor, Balazs [1 ]
Kollar, Istvan [2 ]
机构
[1] Tech Univ Carolo Wilhelmina Braunschweig, Inst Commun Technol, D-38106 Braunschweig, Germany
[2] Budapest Univ Technol & Econ, Dept Measurement & Informat Syst, H-1521 Budapest, Hungary
基金
匈牙利科学研究基金会;
关键词
ADC test; analog-to-digital converter (ADC); effective number of bits (ENOB); elimination of samples; IEEE Standard 1241-2000; least-squares (LS) fit; noise estimation; sine wave fitting; sine wave test;
D O I
10.1109/TIM.2008.928404
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
An important method for analog-to-digital-converter (ADC) testing is sine wave fitting. In this method, the device is excited with a sine wave, and another sine wave is fitted to the samples at the output of the ADC. The acquisition device can be analyzed by looking at the differences between the fitted signal and the samples. The fit is done using the least-squares (LS) method. If the samples of the error (the difference between the fitted signal and the samples) were random and independent of each other and of the signal, the LS fit would have very good properties. However, when the error is dominated by quantization error, particularly when a low bit number is used or the level of the measured noise is low, these conditions are not fulfilled. The estimation will be biased, and therefore, it must be corrected. The independence of the error samples is more or less true if the sine wave is noisy or dither is used. In these cases, the correction is not necessary. Therefore, it is reasonable to analyze the effect of the potentially unnecessary correction to noisy data, and it is desirable to determine the magnitude of the noise from the measurements. In this paper, these two questions are investigated. The variance of the corrected estimator. is investigated, and a new noise estimation method is developed and analyzed.
引用
收藏
页码:2762 / 2768
页数:7
相关论文
共 50 条
  • [41] CAD for verification testing
    Walsh, P
    Hoffman, D
    1997 CANADIAN CONFERENCE ON ELECTRICAL AND COMPUTER ENGINEERING, CONFERENCE PROCEEDINGS, VOLS I AND II: ENGINEERING INNOVATION: VOYAGE OF DISCOVERY, 1997, : 724 - 727
  • [42] Verification and compliance testing
    Guerin, F
    Pitt, J
    COMMUNICATION IN MULTIAGENT SYSTEMS: AGENT COMMUNICATION LANGUAGES AND CONVERSATION POLICIES, 2003, 2650 : 98 - 112
  • [43] Verification, Testing and Statistics
    Rajamani, Sriram K.
    THEORETICAL ASPECTS OF COMPUTING - ICTAC 2009, 2009, 5684 : 79 - 79
  • [44] Verification, Testing and Statistics
    Rajamani, Sriram K.
    FM 2009: FORMAL METHODS, PROCEEDINGS, 2009, 5850 : 33 - 40
  • [45] Verification, Testing and Statistics
    Rajamani, Sriram K.
    RUNTIME VERIFICATION, 2009, 5779 : 25 - 25
  • [46] Measuring and evaluating dynamic ADC parameters - Dynamic ADC testing, Part 2
    Hofner, TC
    MICROWAVES & RF, 2000, 39 (13) : 78 - +
  • [47] Calibration of Timing Mismatch in A Two-Channels Time-Interleaved ADC Based on Testing Signal and Its Verification on FPGA
    Liu, Sujuan
    Yang, Shishen
    Lv, Ning
    2016 13TH IEEE INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT), 2016, : 1473 - 1475
  • [48] Design and Verification of a SAR ADC SystemVerilog Real Number Model
    Georgoulopoulos, Nikolaos
    Mamali, Theodora
    Hatzopoulos, Alkis
    JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 2024, 40 (03): : 315 - 328
  • [49] The IP Soft-core design Of ADC And PLD Verification
    Sun JiangFeng
    Chen Feng
    THIRD INTERNATIONAL SYMPOSIUM ON ELECTRONIC COMMERCE AND SECURITY WORKSHOPS (ISECS 2010), 2010, : 14 - 17
  • [50] Simulink Modeling and Performance Verification of a High Resolution Zoom ADC
    Gao, Jie
    Shen, Chongfei
    Yu, Baodong
    Xie, Hongyun
    Chen, Zhijie
    Wan, Peiyuan
    PROCEEDINGS OF 2019 IEEE 13TH INTERNATIONAL CONFERENCE ON ANTI-COUNTERFEITING, SECURITY, AND IDENTIFICATION (IEEE-ASID'2019), 2019, : 320 - 323