The VCUSRC II: A full-custom VLSI 32-bit RISC processor

被引：1

作者：

Kim, A ^{[1
]}

Weistroffer, GR ^{[1
]}

Grammer, DM ^{[1
]}

Klenke, RH ^{[1
]}

机构：

[1] Virginia Commonwealth Univ, Sch Engn, Dept Elect Engn, Richmond, VA USA

来源：

FOURTEENTH BIENNIAL UNIVERSITY/GOVERNMENT/INDUSTRY MICROELECTRONICS SYMPOSIUM, PROCEEDINGS | 2001年

关键词：

D O I：

10.1109/UGIM.2001.960330

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Heuring and Jordan define a simplified, 32-bit RISC processor instruction set architecture called the Simple RISC Computer. An extended form of this architecture is defined, a gate-level logic design is developed, and a full-custom VLSI implementation is laid out in a 0.5-mum CMOS process, fabricated, and tested. The processor design flow, from ISA definition to IC testing, is carried out by junior- and senior-level undergraduate engineering students over two consecutive semesters as part of an integrated curriculum.

引用

页码：201 / 204

页数：4

共 50 条

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