Accelerating MPSoC Design Space Exploration Within System-Level Frameworks

System on chip designs become more complex every year. The trend goes towards multi and even many core system designs. This means the design space grows steadily with each added component. Furthermore the designers have to meet low power requirements. In order to find good configurations in a reasonable amount of time it is necessary to optimize the design space exploration (DSE) process. In this work we present several DSE algorithms and evaluate them with a range of single and multi core applications. The DSE methodology considers energy delay product (EDP) as overall system performance metric. Our evaluation with several applications shows a reduction in simulation time of approximately 65% while maintaining optimal parameter accuracy of 99% compared to an exhaustive search.