STATS: A framework for microprocessor and system-level design space exploration

被引:0
|
作者
Albonesi, DH
Koren, I
机构
[1] Univ Rochester, Dept Elect & Comp Engn, Rochester, NY 14627 USA
[2] Univ Massachusetts, Dept Elect & Comp Engn, Amherst, MA 01003 USA
关键词
microprocessor design; performance evaluation; memory hierarchies; superscalar processors;
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
As microprocessor-based systems grow in complexity, and the processor-memory speed gap widens further, more emphasis needs to be placed on early design space exploration in order to produce the highest performance systems with minimal schedule impact. We discuss the critical issues associated with architectural evaluation of complex microprocessor-based systems, and present a methodology for the comprehensive and semiautomatic evaluation of processor, cache hierarchy, system interconnect, and main memory architectural and technological alternatives. We discuss the implementation of the methodology, and describe how it can be used in early design space exploration. The unique aspects of the methodology are further illustrated through two architectural investigations performed using the tool-set. (C) 1999 Elsevier Science B.V. All rights reserved.
引用
收藏
页码:1097 / 1110
页数:14
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