Enhancing timing-driven FPGA placement for pipelined netlists

被引：0
|
作者：
Eguro, Ken [1 ]
Hauck, Scott [1 ]
机构：
[1] Univ Washington, Dept Elect Engn, Seattle, WA 98195 USA
来源：
2008 45TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2 | 2008年
关键词：
FPGA; placement; simulated annealing; timing-driven; pipelined;
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
FPGA application developers often use pipelining, C-slowing and retiming to improve the performance of their designs. Unfortunately, registered netlists present a fundamentally different problem to CAD tools, potentially limiting the benefit of these techniques. In this paper we discuss some of the inherent issues pipelined netlists pose to existing timing-driven placement approaches. We then present two algorithmic modifications that reduce post-routing critical path delay by an average of 40%.
引用
收藏
页码：34 / 37
页数：4
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