Investigation of Gate All Around Junctionless Nanowire Transistor with Arbitrary Polygonal Cross Section

被引：0

作者：

Sharma, Monika ^{[1
]}

Gupta, Mridula ^{[1
]}

Narang, Rakhi ^{[2
]}

Saxena, Manoj ^{[3
]}

机构：

[1] Univ Delhi, Dept Elect Sci, Semicond Device Res Lab, South Campus, New Delhi 110021, India

[2] Univ Delhi, Dept Elect, Sri Venkateswara Coll, New Delhi 110021, India

[3] Univ Delhi, Dept Elect, Deen Dayal Upadhyaya Coll, New Delhi 110078, India

来源：

2018 4TH INTERNATIONAL CONFERENCE ON DEVICES, CIRCUITS AND SYSTEMS (ICDCS) | 2018年

关键词：

Analytical model; JNT (Junctionless Nanowire transistor); GAA(Gate All around); MOSFET (Metal oxide Field effect transistor); Simulation; CMOS Inverter;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents an analytical model for the calculation of the potential distribution in junctionless nanowire transistors with an arbitrary regular polygon as a cross-section. Two different cases concerning circular and square cross-sections are particularly investigated and analyzed. Poisson's equation is being solved and electric potential is obtained. With the potential model, an explicit comparison is done between square cross-section GAA transistor and cylindrical GAA transistor which is being further investigated for circuit design and tested for the CMOS inverter application. The proposed model is validated using 3D ATLAS simulations.

引用

页码：159 / 163

页数：5

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