A Zero-IF 60GHz Transceiver in 65nm CMOS with > 3.5Gb/s Links

被引：25

作者：

Tomkins, A. ^{[1
]}

Aroca, R. A. ^{[1
]}

Yamamo, T. ^{[2
]}

Nicolson, S. T. ^{[1
]}

Doi, Y. ^{[2
]}

Voinigescu, S. P. ^{[1
]}

机构：

[1] Univ Toronto, Edward S Rogers Sr Dept Elect & Comp Engn, Toronto, ON M5S 1A1, Canada

[2] Fujitsu Labs Ltd, Kawasaki, Kanagawa, Japan

来源：

PROCEEDINGS OF THE IEEE 2008 CUSTOM INTEGRATED CIRCUITS CONFERENCE | 2008年

关键词：

D O I：

10.1109/CICC.2008.4672123

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a 1.2V 60GHz zero-IF transceiver fabricated in a 65nm CMOS process with a digital back-end. The chip includes a receiver with 14.7dB gain, a low 5.6dB noise figure, a 60GHz LO distribution tree, a 64GHz static frequency divider, and a direct BPSK modulator operating over the 55-65GHz band at data rates exceeding 3.5Gb/s. The chip consumes 374mW (232mW) from 1.2V (1.0V) and occupies 1.28x0.81 mm(2). The transceiver was characterized over temperature up to 85 degrees C and for power supplies down to 1V. A manufacturability, study of 60GHz radio circuits is presented with measurements of transistors, the low-noise amplifier, and the receiver on typical and fast process splits. The transceiver performance is demonstrated using a 3.5Gb/s 2-meter wireless transmit-receive link over the 55-64 GHz range.

引用

页码：471 / +

页数：2

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A Zero-IF 60GHz Transceiver in 65nm CMOS with &gt; 3.5Gb/s Links

A Zero-IF 60GHz Transceiver in 65nm CMOS with > 3.5Gb/s Links