A 60GHz Digitally-assisted Power Amplifier with 17.2dBm PSat, 11.3% PAE in 65nm CMOS

被引：0
|
作者：
Liang, Yuan [1 ]
Li, Nan [1 ,2 ]
Wei, Fei [1 ]
Yu, Hao [1 ]
Li, Xiuping [2 ]
Zhao, Junfeng [3 ]
Yang, Wei [3 ]
Wang, Yuangang [3 ]
机构：
[1] Nanyang Technol Univ, Sch Elect & Elect Engn, Singapore 639798, Singapore
[2] Beijing Univ Posts & Telecommun, Sch Elect Engn, Beijing 100088, Peoples R China
[3] Huawei Technol Co Ltd, Hangzhou 310051, Zhejiang, Peoples R China
来源：
2015 IEEE MTT-S INTERNATIONAL MICROWAVE SYMPOSIUM (IMS) | 2015年
关键词：
D O I：
暂无
中图分类号：
TP301 [理论、方法];
学科分类号：
081202 ;
摘要：
A digitally-assisted CMOS 60GHz PA is reported with high output power and improved power efficiency during power back-off. To combine large number of CMOS power transistors within compact area, a 2D distributed in-phase power combiner is utilized. Moreover, digitally-assisted self-tuning biasing is introduced for power back-off efficiency improvement, where DC power is reduced along with output power. One digitally-assisted 4-way power-combined PA prototype was implemented in 65nm CMOS process with measured output power of 17.2dBm, PAE of 11.3%, and up to 170 similar to 190% efficiency improvement during power back-off for the entire 7GHz band at 60GHz.
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页数：4
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