Intrinsic Capacitance Extraction and Estimation for System-On-Chip Power Delivery Development

被引：0

作者：

Quek, Li Chuang ^{[1
]}

Cheah, Bok Eng ^{[1
]}

Lee, Wai Ling ^{[1
]}

Sam, Weng Chong ^{[1
]}

机构：

[1] Intel Microelect M Sdn Bhd, Bayan Lepas FIZ, Halaman Kampung Jawa 11900, Penang, Malaysia

来源：

2012 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS) | 2012年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents the methodology of on-die parasitic intrinsic capacitance extraction and estimation at the early phase of system-on-chip (SOC) design and development cycle. Accurate estimation of the intrinsic capacitance is critical to prevent circuit overdesign and additional on-die decoupling capacitance requirements that could result in larger silicon footprint. The correlation of the simulated results and silicon measurement data is presented and further discussed in this study. Impacts of intrinsic capacitance to the power delivery capacitance and overall intellectual property (IP) block design optimization are also enveloped in this paper.

引用

页码：388 / 391

页数：4

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