A Complete On-chip Evolvable Hardware Technique Based on Pareto Dominance

被引：0

作者：

Liang, Qingzhong ^{[1
]}

Fan, Yuanyuan ^{[1
]}

Zeng, Sanyou ^{[1
]}

机构：

[1] China Univ Geosci, Sch Comp Sci, Wuhan, Peoples R China

来源：

COMPUTATIONAL INTELLIGENCE AND INTELLIGENT SYSTEMS | 2012年 / 316卷

关键词：

Intrinsic Evolvable Hardware; Multi-objective Algorithm;

D O I：

暂无

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

To increase the speed of evolvable hardware, a complete on-chip evolvable hardware technique is adopted, where both hardware evaluation and evolutionary algorithm itself are configured on chip. At the same time, a multi-objective evolutionary algorithm based on Pareto dominance is proposed to satisfy and conciliate multiple objectives in many combinational circuits design. This method is applied to the design of a 1-bit full adder and its feasibility is validated by the result of the experiment. The data of result also shows that the speed of evolvable hardware is dramatically increased.

引用

页码：258 / 266

页数：9

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