A low-power single-ended SRAM in FinFET technology

被引：52

作者：

Ensan, Sina Sayyah ^{[1
]}

Moaiyeri, Mohammad Hossein ^{[2
]}

Moghaddam, Majid ^{[2
]}

Hessabi, Shaahin ^{[1
]}

机构：

[1] Sharif Univ Technol, Dept Comp Engn, Tehran 111559517, Iran

[2] Shahid Beheshti Univ, GC, Dept Elect Engn, Tehran 1983963113, Iran

来源：

AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS | 2019年 / 99卷

关键词：

SRAM; Single-ended structure; Low-power design; Near-threshold operation; ULTRA-LOW-POWER; SUBTHRESHOLD SRAM; SENSE-AMPLIFIER; BIT-LINE; READ; CELL; DESIGN;

D O I：

10.1016/j.aeue.2018.12.015

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a single-ended low-power 7T SRAM cell in FinFET technology. This cell enhances read performance by isolating the storage node from the read path. Moreover, disconnecting the feedback path of the cross-coupled inverters during the write operation enhances WSNM by nearly 7.7X in comparison with the conventional 8T SRAM cell. By using only one bit-line, this cell reduces power consumption and PDP compared to the conventional 8T SRAM cell by 82% and 35%, respectively. (C) 2018 Elsevier GmbH. All rights reserved.

引用

页码：361 / 368

页数：8

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