A Dynamically Reconfigurable Platform for High-Performance and Low-Power On-Board Processing

被引:0
|
作者
Guerrieri, Andrea [1 ]
Kashani-Akhavan, Sahand [1 ]
Lombardi, Pasquale [2 ]
Belhadj, Bilel [2 ]
Ienne, Paolo [1 ]
机构
[1] Ecole Polytech Fed Lausanne, Architecture Lab, Lausanne, Switzerland
[2] Syderal SA, Gals, Switzerland
关键词
SoC; FPGA; COTS; dynamic partial reconfiguration; software thread; hardware accelerator;
D O I
暂无
中图分类号
V [航空、航天];
学科分类号
08 ; 0825 ;
摘要
FPGAs (Field Programmable Gate Array) are an attractive technology for high-speed data processing in space missions due to their unbeatable flexibility and best performance-to-power ratio in comparison to software. However FPGAs suffer from 3 major drawbacks: (1) higher programming effort is required with respect to software; (2) hardware resources need to be allocated for each implemented function in contrast to software functions which can be executed on the same processing hardware; and (3) FPGAs are required to adopt radiation hardening techniques when deployed in a space environment. This paper presents a reconfigurable platform that demonstrates how modern FPGAs can be considered as computing resources like any other, suitable for emerging spatial applications and not subjected to the above-mentioned drawbacks. In particular, we show that large FPGAs can be split in different regions containing concurrently-running accelerators which can support the execution of a single or multiple applications. Then, in the same way as software-based multiprogrammed and multithreaded systems can dynamically create, schedule and execute threads, FPGA-based accelerators can be swapped in and out according to scheduling needs by exploiting their dynamic partial reconfiguration capability. A proof of concept cloud detection algorithm for Sentinel-2 multispectral images has been implemented and tested on our platform to validate the system's design principles and performance.
引用
收藏
页码:74 / 81
页数:8
相关论文
共 50 条
  • [41] Reconfigurable processing: The solution to low-power programmable DSP
    Rabaey, JM
    1997 IEEE INTERNATIONAL CONFERENCE ON ACOUSTICS, SPEECH, AND SIGNAL PROCESSING, VOLS I - V: VOL I: PLENARY, EXPERT SUMMARIES, SPECIAL, AUDIO, UNDERWATER ACOUSTICS, VLSI; VOL II: SPEECH PROCESSING; VOL III: SPEECH PROCESSING, DIGITAL SIGNAL PROCESSING; VOL IV: MULTIDIMENSIONAL SIGNAL PROCESSING, NEURAL NETWORKS - VOL V: STATISTICAL SIGNAL AND ARRAY PROCESSING, APPLICATIONS, 1997, : 275 - 278
  • [42] LOW POWER HIGH-PERFORMANCE COMPUTING ON THE BEAGLEBOARD PLATFORM
    Principi, Emanuele
    Colagiacomo, Vito
    Squartini, Stefano
    Piazza, Francesco
    2012 5TH EUROPEAN DSP EDUCATION AND RESEARCH CONFERENCE (EDERC), 2012, : 35 - 39
  • [43] A low-power high-performance digital predistorter for wideband power amplifiers
    Manyam V.N.
    Pham D.-K.G.
    Jabbour C.
    Desgreys P.
    Analog Integrated Circuits and Signal Processing, 2018, 97 (03) : 483 - 492
  • [44] Mission-specific processing techniques enable low-power, high-performance surveillance sensors
    Lucas, M
    Shanbhag, N
    Roy, K
    Kurdahi, F
    Fagan, A
    IEEE CIRCUITS & DEVICES, 2004, 20 (04): : 22 - 30
  • [45] A reconfigurable computing board for high performance processing in space
    Van Buren, D
    Murray, P
    Langley, T
    2004 IEEE AEROSPACE CONFERENCE PROCEEDINGS, VOLS 1-6, 2004, : 2316 - 2326
  • [46] FDR 2.0: A Low-Power Dynamically Reconfigurable Architecture and Its FinFET Implementation
    Lin, Ting-Jung
    Zhang, Wei
    Jha, Niraj K.
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2015, 23 (10) : 1987 - 2000
  • [47] A high-performance low-power CMOS AGC for GPS application
    雷倩倩
    许奇明
    陈治明
    石寅
    林敏
    贾海珑
    半导体学报, 2010, 31 (02) : 49 - 53
  • [48] Design of Low-Power High-Performance FinFET Standard Cells
    Wang, Tian
    Cui, Xiaoxin
    Liao, Kai
    Liao, Nan
    Yu, Dunshan
    Cui, Xiaole
    CIRCUITS SYSTEMS AND SIGNAL PROCESSING, 2018, 37 (05) : 1789 - 1806
  • [49] Custom Design in a Low-Power/High-Performance ASIC World
    Garibay, Ty
    Reis, Richard
    2009 IEEE INTERNATIONAL CONFERENCE ON INTEGRATED CIRCUIT DESIGN AND TECHNOLOGY, PROCEEDINGS, 2009, : 1 - 2
  • [50] A high-performance,low-power ∑△ ADC for digital audio applications
    罗豪
    韩雁
    张泽松
    韩晓霞
    马绍宇
    应鹏
    朱大中
    半导体学报, 2010, 31 (05) : 114 - 120