Gate-stack analysis for 45-nm CMOS devices from an RF perspective

Three gate stacks for the 45-nm node are analyzed from an RF perspective. The authors present an expression of the gate resistance valid for all three stacks, quantify the differences each stack has on several small-signal RF figures-of-merit and on the RF noise parameters, and demonstrate that devices with fully silicided gates will enable ultralow-power/low-noise RF applications, while the performance of transistors using multilayer gate stacks are limited by large contact resistance. Although offering better bandwidth and noise characteristics than the poly/silicide stack, the deposited metal stack will lose its advantage in devices requiring higher gate work functions than in planar bulk CMOS transistors.