The Optimization of Spacer Engineering for Capacitor-Less DRAM Based on the Dual-Gate Tunneling Transistor

被引：6

作者：

Li, Wei ^{[1
]}

Liu, Hongxia ^{[1
]}

Wang, Shulong ^{[1
]}

Chen, Shupeng ^{[1
]}

Wang, Qianqiong ^{[1
]}

机构：

[1] Xidian Univ, Sch Microelect, Key Lab Wide Band Gap Semicond Mat & Devices Educ, Xian 710071, Shaanxi, Peoples R China

来源：

NANOSCALE RESEARCH LETTERS | 2018年 / 13卷

基金：

中国国家自然科学基金;

关键词：

Tunneling FET (TFET); DRAM; Spacer engineering; Retention time; RETENTION TIME; 1T-DRAM CELL; LOW-POWER; GENERATION;

D O I：

10.1186/s11671-018-2483-8

中图分类号：

TB3 [工程材料学];

学科分类号：

0805 ; 080502 ;

摘要：

The DRAM based on the dual-gate tunneling FET (DGTFET) has the advantages of capacitor-less structure and high retention time. In this paper, the optimization of spacer engineering for DGTFET DRAM is systematically investigated by Silvaco-Atlas tool to further improve its performance, including the reduction of reading "0" current and extension of retention time. The simulation results show that spacers at the source and drain sides should apply the low-k and high-k dielectrics, respectively, which can enhance the reading "1" current and reduce reading "0" current. Applying this optimized spacer engineering, the DGTFET DRAM obtains the optimum performance-extremely low reading "0" current (10-14A/mu m) and large retention time (10s), which decreases its static power consumption and dynamic refresh rate. And the low reading "0" current also enhances its current ratio (107) of reading "1" to reading "0". Furthermore, the analysis about scalability reveals its inherent shortcoming, which offers the further investigation direction for DGTFET DRAM.

引用

页数：9

共 50 条

[1] The Optimization of Spacer Engineering for Capacitor-Less DRAM Based on the Dual-Gate Tunneling Transistor
Wei Li
Hongxia Liu
Shulong Wang
Shupeng Chen
Qianqiong Wang
Nanoscale Research Letters, 2018, 13
[2] Ferroelectric-gate transistor as a capacitor-less DRAM cell (FEDRAM)
Han, JP
Ma, TP
INTEGRATED FERROELECTRICS, 1999, 27 (1-4) : 1053 - 1062
[3] Capacitor-less 1-Transistor DRAM
Fazan, P
Okhonin, S
Nagoga, M
Sallese, JM
Portmann, L
Ferrant, R
Kayal, M
Pastre, M
Blagojevic, M
Borschberg, A
Declercq, M
2002 IEEE INTERNATIONAL SOI CONFERENCE, PROCEEDINGS, 2002, : 10 - 13
[4] A 2T Dual Port Capacitor-Less DRAM
Li, Hui
Lin, Yinyin
IEEE ELECTRON DEVICE LETTERS, 2014, 35 (02) : 187 - 189
[5] Design and investigation of dopingless dual-gate tunneling transistor based on line tunneling
Li, Wei
Liu, Hongxia
Wang, Shulong
Chen, Shupeng
Han, Tao
Yang, Kun
AIP ADVANCES, 2019, 9 (04)
[6] FEDRAM: A Capacitor-less DRAM Based on Ferroelectric-Gated Field-Effect Transistor
Ma, T. P.
2008 9TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED-CIRCUIT TECHNOLOGY, VOLS 1-4, 2008, : 850 - 852
[7] FEDRAM: A Capacitor-less DRAM Based on Ferroelectric-Gated Field-Effect Transistor
Ma, T. P.
2014 IEEE 6TH INTERNATIONAL MEMORY WORKSHOP (IMW), 2014,
[8] Analysis of Single Event Effects in Capacitor-Less 1T-DRAM Based on an InGaAs Transistor
Yan, Gangping
Xi, Kai
Xu, Gaobo
Bi, Jinshun
Yin, Huaxiang
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2021, 68 (04) : 1604 - 1609
[9] Investigation of capacitor-less integrate and fire neuron by using dual-gate a PN-body tied silicon on insulator field-effect transistor
Mori, Takayuki
Ida, Jiro
JAPANESE JOURNAL OF APPLIED PHYSICS, 2021, 60 (SB)
[10] SOI capacitor-less 1-transistor DRAM sensing scheme with automatic reference generation
Blagojevic, M
Pastre, M
Kayal, M
Fazan, P
Okhonin, S
Nagoga, M
Declercq, M
2004 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 2004, : 182 - 183

← 1 2 3 4 5 →