Analysis and equalization of data-dependent jitter

被引:20
|
作者
Buckwalter, JF [1 ]
Hajimiri, A [1 ]
机构
[1] CALTECH, Pasadena, CA 91125 USA
基金
美国国家科学基金会;
关键词
data-dependent jitter; equalizer; jitter; timing circuits;
D O I
10.1109/JSSC.2005.864119
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Data-dependent jitter limits the bit-error rate (BER) performance of broadband communication systems and aggravates synchronization in phase-and delay-locked loops used for data recovery. A method for calculating the data-dependent jitter in broadband systems from the pulse response is discussed. The impact of jitter on conventional clock and data recovery circuits is studied in the time and frequency domain. The deterministic nature of data-dependent jitter suggests equalization techniques suitable for high-speed circuits. Two equalizer circuit implementations are presented. The first is a SiGe clock and data recovery circuit modified to incorporate a deterministic jitter equalizer. This circuit demonstrates the reduction of jitter in the recovered clock. The second circuit is a MOS implementation of a jitter equalizer with independent control of the rising and falling edge timing. This equalizer demonstrates improvement of the timing margins that achieve 10(-12) BER from 30 to 52 ps at 10 Gb/s.
引用
收藏
页码:607 / 620
页数:14
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